Volatile memory resources find widespread usage in current computing platforms, whether for servers, desktop or laptop computers, mobile devices, and consumer and business electronics. DRAM (dynamic random access memory) devices are the most common types of memory devices in use. However, DRAM errors are projected to increase as the manufacturing processes to produce the DRAMs continue to scale to smaller geometries. One technique for addressing the increasing DRAM errors is to employ on-die ECC (error checking and correction). On-die ECC refers to error detection and correction logic that resides on the memory device itself. With on-die ECC logic, a DRAM can correct single bit failures, such as through a single error correction (SEC) or single error correction, dual error detection (SECDED) techniques. On-die ECC can be used in addition to system level ECC, but the system level ECC has no insight into what error correction has been performed at the memory device level. However, providing details of error correction performed by the DRAM would expose sensitive data about the design and operation of the DRAMs.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.